1. Field of the Invention
The present invention relates to a pulse width modulation signal generating apparatus for controlling a power supply of a copier or the like.
2. Related Background Art
A pulse width modulation (PWM) signal generator has been proposed which in order to generate stable low and high voltage outputs from a switching power supply having a single transformer, generates a main PWM signal (hereinafter called a "first PWM signal") for low voltage outputs and a main synchronism sub PWM signal (hereinafter called a "second PWM signal") for high voltage outputs, the second PWM signal synchronizing with the first PWM signal.
FIGS. 13A, 13B, 14 and 15 are block diagrams of a PWM signal generator according to a first related art. In these Figures, reference numeral 1 to 6 represent an 8-bit latch (register) whose output terminals are connected via clocked buffers (B.F.) 11 to 16 to a bus 65. The outputs of the latches 1 and 2 are inverted by inverters 55 and 54 (FIGS. 2A and 2B) and supplied to a bus 64. The output terminals of latches 7 and 8 are connected via clocked buffers (B.F.) 19 and 20 to the bus 64. The input terminals of the latches 1 to 8 are connected to a bus 75. The bus lines 64 and 65 are connected to different input terminals of an adder 63 whose output terminal is connected via a bus 66 to the input terminals of latches 9 and 10, and via the bus 66 and a clocked buffer (B.F.) 74 to a bus 75. The bus 75 is connected via a clocked buffer (B.F.) 25 to a CPU bus 73. The output terminals of the latches 9 and 10 are connected via respective buses 67 and 68 and clocked buffers (CLK B.F.) 23 and 24 to a bus 69, and via clocked buffers 22 and 21 to the bus 64. Reference numeral 26 represents an UP free-run counter (FIG. 3) whose count output terminal is connected via a bus 70 to one input terminal of a digital comparator 27. The other input terminal of the digital comparator 27 is connected to the bus 69. Reference numerals 29 and 30 represent a synchronism T-type flip-flop (hereinafter designated as "TFF") operating in a toggle manner. The Q output terminals of TFFs 29 and 30 are connected to respective output terminals PWM1.multidot.OUT and PWM2.multidot.OUT, the clock input terminals thereof are connected to a signal line TSET, and the data input terminals thereof are connected to the output terminals of respective two-input AND gates 41 and 42. Of the input terminals of the two-input AND gates 41 and 42, one input terminals are both connected to the output terminal of the digital comparator 27, and the other input terminals are connected to signal lines SUM1O and SUM2O. Reference numerals 31 and 32 represent a D-latch whose data input terminals D are connected to the carry output terminal of the adder 63 and whose latch signal input terminals are connected to the output terminals of respective two-input AND gates 38 and 39. One input terminals of the two-input AND gates 38 and 39 are connected to a signal line TSET connected to the clock input terminal of the adder 63 and the other input terminals are connected to respective signal lines PM10FS and PM2OFS. The Q output terminals of the D-latches 31 and 32 are connected to the one input terminals of two-input AND gates 35 and 36 and to the input terminals of inverters 56 and 67. Reference numeral 51 (FIG. 2A) represents an analog comparator whose minus input terminal is connected to the output terminal of a reference power source 52 with one end being grounded and whose plus input terminal is supplied with a signal FBIN1 of a control information detector of an external control circuit. The output terminal of the analog comparator 51 is connected to the data input terminal of a D-type flip-flop (hereinafter called a "DFF") 28. The Q output terminal of DFF 28 is connected to one input terminal of a two-input gate 33, and the Q output terminal thereof is connected to one input terminal of a two-input gate 34. The other input terminals of the two-input gates 33 and 34 are both connected to a signal line PM10NS, and the output terminals thereof are connected one input terminals of two-input OR gates 81 and 82 and to signal input terminals UP1 and DW1 of a 1H detector circuit (FIGS. 1A and 1B) 61. Reference numeral 51-2 represents another analog comparator whose minus input terminal, like the analog comparator 51, is connected to the output terminal of another reference power source 52-2 with one end being grounded and whose plus input terminal is supplied with a signal FBIN2 of the control information detector of the external control circuit. The output terminal of the analog comparator 52 is connected to the data input terminal of another DFF 28-2. The Q output terminal of DFF 28-2 is connected to one input terminal of a two-input gate 33-2, and the Q output terminal thereof is connected to one input terminal of a two-input AND gate 34-2. The other input terminals of the two-input AND gates 33-2 and 34-2 are both connected to a signal line PM20NS. The output terminals of the two-input AND gates 33-2 and 34-2 are connected to the other input terminals of respective two-input OR gates 81 and 82 and to UP2 and DW2 signal input terminals of the 1H detector circuit 62. The output terminals of the two-input OR gates 81 and 82 are connected respective signal control terminals of the clocked buffers 20 and 19. The other input terminals of the two-input AND gates 35 and 36 are connected to signal lines CHG1ON and CHG2ON and the output terminals thereof are connected to the control terminals of the clocked buffers 11 and 12. The control signal input terminals of the latches 9 and 10 for PWM1 and PWM2 signals are connected to the output terminals of respective two-input AND gates 40 and 37. One input terminals of the two-input AND gates 40 and 37 are both connected to the signal line TSET, and the other input terminals are connected to the signal lines CHG1 and CHG2. Reference numerals 47 and 48 represent a two-input AND gate whose one input terminals are connected to respective signal lines CHG1ON and CHG2ON and whose other input terminals are connected to the output terminals of inverters 56 and 57. Reference numerals 49 and 50 represent a three-input OR gate whose one input terminals are connected to the output terminals of the two-input AND gates 47 and 48. The other two input terminals of the three-input OR gate 49 are connected to signal lines PM1OFS and PM1ONS and the other two input terminals of the three-input OR gate 50 are connected to signal lines PM2OFS and PM2ONS. The output terminals of the three-input OR gates 49 and 50 are connected to the control terminals of the clocked buffers 13 and 14. One input terminals of two-input AND gates 43 and 44 are both connected to the signal line TSET and the other input terminals thereof are connected to the signal lines PM1ONS and PM2ONS. The output terminals of the two-input AND gates 43 and 44 are connected to one input terminals of respective two-input OR gates 45 and 46 whose other input terminals are connected to respective signal lines ON1SET and ON2SET. The output terminals of the two-input OR gates 45 and 46 are connected to the latch input terminals of the latches 3 and 4. The latch control terminals of the latches 1, 2, 5, and 6 are connected to respective signal lines MAXSET1, MAXSET2, CPUSET1, and CPUSET2. The control terminals of the clocked buffers 15, 16, 17, 18, 21, 22, 23, and 24 are connected to respective signal lines PM1OFO, PM2OFO, PM2OFS, PM1OFS, CHG2, CHG1, SUM1O and SUM 20. The control terminals of the clocked buffers 25 and 74 are connected to respective Q and Q output terminals of a D-latch 80 which serves as a flag of CPU. The latch input terminal of the D-latch 80 is supplied with an address signal and the data input terminal is connected to a signal line through which CPU supplies flag set data. Reference numeral 53 represents a timing circuit (FIG. 3) for generating various signals to be supplied to the above-described signal lines, the timing circuit 53 having an inverter 58, a 1/2 frequency divider 59, and a delay circuit 60. Reference numeral 83 represents a basic clock input terminal which is connected to the input terminal of the 1/2 frequency divider 59 and to the input terminal of the delay circuit 60. The output terminal of the delay circuit 60 is connected to the signal line TSET and to the input terminal of the inverter 58. The output terminal of the 1/2 frequency divider 59 is connected to the clock input terminal of the free-run counter 26. The output terminal of the inverter 58 is connected to the signal line TSET. The timing circuit 53 also has input terminals for the Q output signals from the DFFs 29 and 30. It is assumed that the delay circuit 60 can provide a delay time corresponding to a half period of a period from 0 to .phi.. Reference numerals 61 and 62 represent a 1H detector circuit (FIGS. 1A and 1B) for detecting a 1H digital value whose input terminals are connected to the output buses of the latches 3 and 4. The output signals of the DFFs 28 and 28-2 described above are supplied to the control signal input terminals of the 1H detector circuits 61 and 62. The output signal lines of the 1H detector circuits are connected to the reset input terminals of the latches 3 and 4. The detailed structure of the inverters 54 and 55 is shown in FIG. 16.
Next, the operation of the PWM signal generator of the first related art will be described with reference to FIGS. 17 and 18.
FIG. 17 is a basic timing chart of the first related art. Although not shown in the block diagrams of FIGS. 13A, 13B, 14A and 14B and 15, all the latches, flip-flops, and counters are reset to OH (0 of hexadecimal) when the operation starts.
The UP free-run counter 26 counts up by 1 starting from 0 and when the count reaches FFH it is reset to 0 (Steps S1 and S3). The fundamental operation of generating a PWM signal is as follows. In the case of the first pulse (PWM signal at the output terminal PWM1.multidot.OUT), each time the data of the PWM1 latch 9 coincides with the value of the UP free-run counter 26 the adder 63 adds alternately the on-data representative of the on-period of the PWM signal or the off-data representative of the off-period of the PWM signal to the value of the UP free-run counter 26, the addition result is again set to the latch 9 (Steps S2 and S4), and the value of the on-data added with or subtracted by "1" (Step S5) is compared with a MAX limiter value (Steps S6 and S7). The above Steps are repeated. The on- and off-data to be added to the counter value are in the latches 3 and 5. At the timings of CHG1ON and PWM1OFO, the clocked buffers 13 and 15 are made through so that the on- or off-data is added to the value of the latch 9 and the result is again set to the latch 9.
A simplified flow chart of the processes regarding the PWM1 signal is shown in FIG. 18.
In the case of the second pulse (PWM signal at the output terminal PWM2.multidot.OUT), like in the case of the first pulse, each time the data of the PWM2 latch 10 coincides with the value of the UP free-run counter 26, the adder 63 adds alternately the on-data representative of the on-period of the PWM signal or the off-data representative of the off-period of the PWM signal to the value of the UP free-run counter 26, the addition result is again set to the latch 10, and the value of the on-data added with or subtracted by "1" is compared with the MAX limiter value. The above operations are repeated. The on- and off-data to be added to the counter value are in the latches 4 and 6. At the timings of CHG2ON and PWM2OFO, the clocked buffers 14 and 16 are made through so that the on- or off-data is added by the adder 63 to the value of the latch 10 and the result is again set to the latch 10.
The circuit for the second pulse is designed so that at the same timing when the data of the latch 9 coincides with the data of the counter 26, the adder 63 adds the data of the latch 10 to the data of the latch 4 or 6 and the addition result is again set to the latch 10. Similarly, the circuit for the first pulse is designed so that at the same timing when the data of the latch 10 coincides with the data of the counter 26, the adder 63 adds the data of the latch 9 to the data of the latch 3 or 5 and the addition result is again set to the latch 9. This addition operation is always performed always only at the timing immediately after the inversion of the output value at the output terminal PWMI.multidot.OUT or PWM2.multidot.OUT or at the timing when a comparator coincidence signal is not generated, i.e., at timings of CHG1ON, CHG2ON, PM1OFO, and PWM2OFO shown in FIG. 17.
For the above control, it is necessary to properly switch the data of the clocked buffers 13, 14, 15, 16, 21, 22, 23, and 24. Control signals used for this purpose are shown in the timing chart of FIG. 17. Specifically, the control signals include CHG1ON, CHG2ON, PWlOFO, PW20FO, CHG2, CHG1, SUM1O, and SUM2O. The adder 63 operates to set the addition result to its output terminal at each rise timing of the TSET signal, and operates to output the addition result to the bus line 66. In other words, the adder 63 is made of one module of a usual adder and a D-type flip-flop. The latch 9 is supplied with a control signal from the two-input AND gate 40 which control signal is a logical product of the signals TSET and CHG1, whereas the latch 10 is supplied with a control signal from the two-input AND gate 37 which control signal is a logical product of the signals TSET and CHG2. The clocked buffers 23 and 24 are supplied with the control signals SUM1O and SUM2O, respectively, to allow the above complicated control to be operable in a time division manner.
CHG1 and CHG2 are generated at the timing of 31.25 ns immediately after the signals PWM1 and PWM2 are inverted. CHG1 is a logical sum of CHG1ON and PM1OFO, whereas CHG2 is a logical sum of CHG2ON and PM2OFO.
A comparison result of the digital comparator 27 is outputted to the signal line 71. The output signals of the two-input AND gates 41 and 42 are supplied to the T input terminals of the T-type flip-flops 29 and 30 at the timing of the signal TSET. The signals are inverted by the flip-flops 29 and 30 to output correct PWM signals from the output terminals PWMI.multidot.OUT and PWM2.multidot.OUT.
Although all the latches, counters, comparators, and adders shown in FIGS. 13A, 13B, 14A, 14B and 15 are assumed to be an 8-bit configuration for the convenience of description, the bit size may be set as desired. The timing chart shown in FIG. 17 is assumed that 3H data is set to the PWM1 latch 3 and PWM2 latch 4.
The initial values of respective circuit portions are set as in the following. An unrepresented CPU for controlling the power supply turns the flag 80 on to make the clocked buffer be through and the clocked buffer 74 be in a high impedance state. Thereafter, CPU applies data setting signals each constituted by an address signal and a strobe signal to the signal lines MAXSET1, MAXSET2, ON1SET, ON2SET, CPUSET1, and CPUSET2, and sets desired data to the latches 1 to 6 via the buses 73 and 75. Thereafter, CPU sets "0" to the flag 80 to make the clocked buffer 74 be through and the clocked buffer be in a high impedance state.
Next, the control of an on-width of the PWM signal will be described. This control is performed by using the adder 63 at the timings of PM1ONS and PM2ONS while the digital comparator 27 does not output a coincidence signal, i.e., during the off (O) period of the PWM signal.
With the on-width feedback control of the PWM1 signal, the on-width of the PWM1 signal is made narrower to make the value of FBIN1 smaller if Vref &lt;FBIN1 where Vref1 represents a comparison reference voltage of the analog comparator 51 and FBIN1 represents an external feedback signal, and if Vref1 &gt;FBIN1 the on-width of the PWM1 signal is made wider to make the value of FBIN1 larger.
The output value of the analog comparator 51 is sampled by the D-type flip-flop (DFF) 28 synchronously with CMP.multidot.CLK1 (replaceable by PM1OFS). If the output value is H, the Q output of DFF 28 is H, whereas if the output value is L, the Q output is L. When the Q output of DFF 28 is H, the clocked buffer 19 is selected and made through and the clocked buffer 20 is made in a high impedance state, by the gates 33, 34, 81, and 82 at the timing when the signal PM1ONS becomes H. Conversely, when the Q output of DFF 28 is L, the clocked buffer 20 is selected and made through and the clocked buffer 19 is made in a high impedance state, by the gates 33, 34, 81, and 82 at the timing when the signal PM1ONS becomes H. Specifically, in order to widen the on-width, the adder 63 adds O1H data in the latch 8 to the value of the latch 3, and the addition result is again written in the latch 3 to increment the value of the latch 3 by 1. In order to narrow the on-width, the adder 63 adds FFH data in the latch 7 to the value of the latch 3, and the addition result is again written in the latch 3 to decrement the value of the latch 3 by 1.
Similarly, with the on-width feedback control of the PWM2 signal, the on-width of the PWM2 signal is made narrower to make the value of FBIN2 smaller if Vref2&lt;FBIN2 where Vref2 represents a comparison reference voltage of the analog comparator 51-2 and FBIN2 represents an external feedback signal, and if Vref2&gt;FBIN2 the on-width of the PWM2 signal is made wider to make the value of FBIN2 larger.
The output value of the analog comparator 51-2 is sampled by DFF 28-2 synchronously with CMP.multidot.CLK2 (replaceable by PM2OFS). If the output value is H, the Q output of DFF 28-2 is H, whereas if the output value is L, the Q output is L.
When the Q output of DFF 28-2 is H, the clocked buffer 19 is selected and made through and the clocked buffer 20 is made in a high impedance state, by the gates 33, 34, 81, and 82 at the timing when the signal PM2ONS becomes H. Conversely, when the Q output of DFF 28 is L, the clocked buffer 20 is selected and made through and the clocked buffer 19 is made in a high impedance state, by the gates 33, 34, 81, and 82 at the timing when the signal PM2ONS becomes H. Specifically, in order to widen the on-width of the PWM signal, the adder 63 adds O1H data in the latch 8 to the value of the latch 4, and the addition result is again written in the latch 4 to increment the value of the latch 4 by 1. In order to narrow the on-width, the adder 63 adds FFH data in the latch 7 to the value of the latch 4, and the addition result is again written in the latch 4 to decrement the value of the latch 4 by 1.
For the above controls, PM1ONS and TSET signals are supplied via the two-input AND gate 43 and OR gate 45 to the latch 3 which stores the control data of the on-width of the PWM1 signal, and PM1ONS signal is supplied via the OR gate 49 to be buffer 13. Similarly, PM2ONS and TSET signals are supplied via the two-input AND gate 44 and OR gate 46 to the latch 4 which stores the control data of the on-width of the PWM2 signal, and PM2ONS signal is supplied via the OR gate 50 to be buffer 14. CMP.multidot.CLK1 sampling signal may be another signal if it synchronizes with PM1ONS, and CMP.multidot.CLK2 sampling signal may be another signal if it synchronizes with PM2ONS.
By changing the values of the latches 8 and 7, the on-width to be made wider or narrower can be set as desired.
Next, the control of a pulse maximum value (maximum on-width) limiter will be described. This control also uses the PWM signal off (O) period, more in particular, uses the adder 63 at the timings of PM1OFS and PM2OFS.
In the case of the PWM1 signal, the inverted values of the value of the latch 3 and the value (maximum pulse width value of the PWM1 signal) of the latch 1 are added together by the adder 63. If the addition result generates a carry, "1" is set to the D-latch 31, and if not, "0" is set to the D-latch 31. The latch timing is a timing when PWM1OFS and TSET signals are supplied via the AND gate 38 to the D-latch 31. If the Q output of the D-latch 31 becomes "1" once, the two-input AND gate 47 turns off and the two-input AND gate 35 turns on so that when the next CHG1ON signal is inputted, the value of the latch 1 is outputted to the bus 65 instead of the value of the latch 3. Therefore, the on-width of the PWM1 signal is always controlled to be set to the maximum value of the on-width set in the latch 1.
Specifically, with this control, if the addition result of the on-width and the inverted value of the maximum width data of the latch 1 becomes larger than the maximum width data of the latch 1, a carry is generated and this information is latched to control the maximum on-width.
If the Q output of the D-latch 31 is "0", one input of the two-input AND gate 47 becomes H and the output of the two-input AND gate 35 becomes L. Therefore, when the next CHG1ON signal is inputted, the value of the latch 3 itself is outputted to the bus 65.
For the bus control, the latches 17 and 18 and clocked buffers 11, 12, 13, and 14 are controlled synchronously with PM2OFS, PM1OFS, CHG1ON, CHG2ON, CHG1ON, and CHG2ON. The inverters 54 and 55 invert all the bits of the latches 2 and 1 and output them to the bus 64 via the clocked buffers 17 and 18. The detail of the inverters 54 and 55 is shown in FIG. 16. The minimum on-width can also be controlled easily in the manner similar to the above.
The minimum on-width detector circuits 61 and 62 detect the minimum on-widths of PWM1 and PWM2 signals. In this example, these circuits detect 1H which is the minimum on-width and control to set the on-width so as not to make it equal to or narrower than the minimum on-width. The circuits 61 and 62 detect the values 1H of the latches 3 and 4, and operate to always set the value of the latches 3 and 4 to 1H when DW1 and DW2 are "1" and UP1 and UP2 are "0", and to release 1H of the latches 3 and 4 when DW1 and DW2 change from "1" to "0" and UP1 and UP2 change from "0" to "1".
In the case of the PWM2 signal, the value of the latch 4 and the value (maximum pulse width value of the PWM2 signal) of the latch 2 are added together by the adder 63. If the addition result generates a carry, "1" is set to the D-latch 32, and if not, "0" is set to the D-latch 32. The latch timing is a timing when PWM2OFS and TSET signals are supplied via the AND gate 39 to the D-latch 32. If the Q output of the D-latch 32 becomes "1" once, the two-input AND gate 48 turns off and the two-input AND gate 36 turns on so that when the next CHG2ON signal is inputted, the value of the latch 2 is outputted to the bus 65 instead of the value of the latch 4. Therefore, the on-width of the PWM2 signal is always controlled to be set to the maximum value of the on-width set in the latch 2.
Specifically, with this control, if the addition result of the on-width and the inverted value of the maximum width data of the latch 2 becomes larger than the maximum width data of the latch 2, a carry is generated and this information is latched to control the maximum on-width.
If the Q output of the D-latch 32 is "0", one input of the two-input AND gate 48 becomes H and the output of the two-input AND gate 36 becomes L. Therefore, when the next CHG2ON signal is inputted, the value of the latch 4 itself is outputted to the bus 65.
The timing circuit 53 generates the above timing signals. A basic clock is applied to a terminal 83, frequency divided by the 1/2 frequency divider 59, and supplied to the clock input terminal of the UP free-run counter 26. The basic clock is delayed by the delay circuit 60 and outputted as TSET signal or inverted by the inverter 58 to be outputted as TSET signal. By using these signals and PWM1 and PWM2 signals, the timing circuit 53 can readily generate all other timing signals through digital differentiation.
FIGS. 19A, 19B, 20A, 20B, and 21 are block diagrams of a PWM signal generator according to a second related art. The fundamental structure and operation are similar to the first related art, and so only different points will be described.
As compared to the first related art, the second related art is provided additionally with a DFF 400 (8 bits) and an OR gate 401. TSET signal is inputted to the inverted clock input terminal of DFF 400. The 8-bit data input terminal of DFF 400 is connected to the 8-bit output terminal of the free-run counter 26, and the Q output terminal thereof is connected to the input terminals of the buffers 21 and 22. These circuit portions are different from the buffers 21 and 22 of the first related art. Furthermore, in the first related art, although one input terminal of the AND gate 41 is directly connected to the output terminal of the digital comparator 27, in the second related art, it is connected via one input terminal of the two-input OR gate 401. The other input terminal of the OR gate 401 is connected to the trigger input terminal 402 to which a trigger signal TIM is supplied externally.
The operation of the second related art will be described.
If the external trigger signal TIM is not used, the first related art without DFF 400 may be used. However, the structure of the first related art without DFF 400 is associated with the following problem. Namely, if an H signal for externally controlling the PWM signal is inputted to the trigger input terminal while the digital comparator 27 does not output a coincidence signal, the values to be re-set to the latches 9 and 10 become incorrect and the circuit operates erroneously because the value of the comparator 27 and the value of the counter 26 are not coincident.
To solve this problem, each time the count of the free-run counter 26 changes by "1", the count of the free-run counter 26 is latched to DFF 400 at the fall timing of TSET signal. Therefore, even if the off-period of the PWM signal is changed instantly by applying the trigger signal TIM to the trigger input terminal 402, the adder 63 can add together the value of DFF 400 and the on- or off-data of the PWM signal and can generate the PWM signal without any malfunction. When the digital comparator 27 outputs the coincidence signal, the value of the free-run counter 26 is latched by DFF 400 and the operation similar to the first related art is performed.
FIGS. 22A and 22B are block diagrams of a PWM signal output unit of a third related art, the unit operating synchronously with an output of the PWM signal of the second related art. FIGS. 23A, 23B, 24A, 24B and 25 are block diagrams of a PWM signal generator unit of the third related art corresponding to that of the second related art. In FIGS. 22A and 22B, identical signals to those shown in FIGS. 23A, 23B, 24A, 24B and 25 are given the same signal names in parentheses as FIGS. 23A, 23B, 24A, 24B and 25, and a signal without a name in parentheses is a newly added signal.
The circuit of the third related art is applied, for example to the case where a switching power supply having a single transformer is used for supplying stable low and high voltage outputs. In such a case, a primary side switching element of the switching power supply is turned on and off by a main PWM signal (first PWM signal) to obtain a stable low voltage output from a low voltage secondary winding, and a secondary side switching element connected to a high voltage secondary winding is turned on and off by a main synchronism sub PWM signal (second PWM signal) to obtain a stable high voltage output from the high voltage secondary winding. Since the main synchronism sub PWM signal is synchronous with the main PWM signal, the circuit can be structured so that the secondary switching element can be turned on and off in a no-voltage state and a loss of the secondary switching element can be reduced.
Since the fundamental structure and operation of the third related art is similar to the second related art, generation of the main synchronism sub PWM signal will be described in correspondence with the second related art. The fundamental circuit portion is called a main circuit.
Referring to FIGS. 22A and 22B, reference symbol 1b represents an 8-bit up-counter and reference symbol 2b represents an 8-bit latch. An output of the adder 63 of the main circuit is supplied to the 8-bit D input terminal of the latch 2b, and the output of the latch 2b is supplied via a transfer buffer 3b to the input bus 65 of the adder 63 of the main circuit. Reference symbol 4b represents an 8-bit inverter which inverts the data latched by the latch 2b and supplies it to the data input terminal of the counter 1b. Reference symbol 5b represents an RS-type flip-flop (hereinafter called an "RSFF"), reference symbol 6b represents an OR gate, and reference symbol 7b represents a latch which prevents the data load release of the data input terminal of the counter 1b from having the same timing as the clock rise timing. Reference symbol 8b represents an inverter, and reference symbol 9b represents a DFF for frequency dividing the system clock and supplying it to the counter 1b. Reference symbol 10b represents a controlled power supply voltage Vin, and reference symbol 11b represents a reference voltage Vref to be compared with the controlled power supply voltage Vin. Reference symbol 12b represents a comparator, reference symbol 13b represents a DFF, and reference symbol 14b represents a composite gate for outputting an NOR of the outputs of two two-input AND gates which intercept an input of a clock to the latch 2b while the maximum/minimum on-width limit operation is performed. Reference symbol 15b represents an AND gate for supplying a clock to the latch 2b, and reference symbol 16b represents an AND gate for outputting an AND of the Q output of the latch 7b and a carry output of the counter 1b. Reference symbol 17b represents an RSFF for outputting the main synchronism sub PWM signal, and reference symbol 18b represents a protect counter (hereinafter simply called a "counter") for setting a predetermined protect period (input inhibition period) in response to an input of an external trigger. Reference symbol 19b represents a frequency divider circuit, and reference symbol 20b represents an RSFF. Reference symbol 21b represents a composite gate, reference symbol 22b represents an AND gate, and reference symbols 23b and 24b represent an inverter. It is assumed that the counter 18b has a bit length sufficient for enabling the protection of the whole "L" period of the maim PWM signal in response to a clock period of the frequency divider circuit 19b.
The circuit connection is as in the following.
The S input terminal of RSFF 5b is connected via the AND gate 22b to an external trigger input terminal (MSTRG), the R input terminal thereof is connected to a main PWML period setting signal line (PM10FO), and the Q output is supplied to one input terminal of the two-input OR gate 6b. The other input terminal of the two-input OR gate 6b is connected to a PMW1OUT signal line, and the output terminal of the OR gate 6b is connected to the D input terminal of the D-latch 7b. The clock input terminal of the D-latch 7b is connected to a main circuit counter clock (SUM2O) signal line, and the Q output terminal thereof is connected to the clock input terminal of the counter 1b and to one input terminal of the two-input AND gate 16b. The other input terminal of the two-input AND gate 16b is connected to a carry signal output terminal of the counter 1b. The output terminal of the two-input AND gate 16b is connected to the S input terminal of RSFF 17b, and the R input terminal of RSFF 17b is connected to the main PWML period setting signal line (PM1OFO). The Q output terminal of RSFF 17b is an output terminal for the main synchronism sub PWM signal. The clock input terminal of the counter 1b is connected to the D input terminal and Q output terminal of DFF 9b. The clock input terminal of DFF 9b is connected to the output terminal of the inverter 8b, and the input terminal of the inverter 8b is supplied with a system clock (TSET). The clock input terminal of the latch 2b is connected to the output terminal of the three-input AND gate 15b. One input terminal of the three-input AND gate 15b is supplied with the system clock (TSET), another input terminal thereof is connected to the output terminal of the composite gate 14b, and the other input terminal thereof is inputted with a data setting signal (PM1ONSS). This data setting signal (PM1ONSS) is also supplied to the input terminal of the transfer buffer 3b and to the clock input terminal of DFF 13b. The input terminal of one AND gate of the composite gate 14b is connected to the Q output terminal of DFF 13b and to the carry output terminal (CRYOUT) of the adder 63 of the main circuit, and the input terminal of the other AND gate is connected to the Q output terminal of DFF 13b and to the output terminal of the inverter 24b. The input terminal of the inverter 24b is connected to the carry output terminal (CRYOUT) of the adder 63 of the main circuit. The Q output terminal of DFF 13b for ST1 signal and the Q output terminal thereof for ST1B signal are connected to the same signal line shown in FIGS. 24A and 24B. The D input terminal of DFF 13b is connected to the output terminal of the comparator 12b, the minus input terminal of the comparator 12b is connected to the output terminal of the reference voltage Vref whose one end being grounded, and the plus input terminal thereof is inputted with the controlled power supply voltage Vin. The carry output terminal of the counter 18b is connected to the S input terminal of RSFF 20b, the clock input terminal of the counter 18b is connected to the output terminal of the composite gate 2lb, and the load terminal thereof is connected to the main PWM signal line (PMW1OUT). This signal line is also connected to the R input terminal of RSFF 20b and to the reset terminal of the frequency divider circuit 19b. The Q output terminal of RSFF 20b is connected to one input terminal of the two-input AND gate 22b whose other input terminal is connected to the external trigger terminal (MSTRG). The output terminal of the two-input AND gate 22b is connected to the S input terminal of RSFF 5b. The clock input terminal of the frequency divider circuit 19b is connected to the output terminal of the inverter 23b whose input terminal is connected to a counter clock signal terminal (SUM2O). The output terminal Qn of the frequency divider circuit 19b is connected to an input terminal of the OR gate of the composite gate 2lb. One input terminal of the AND gate of the composite gate 2lb is connected to the system clock terminal (TSET), and the other input terminal is connected to a main PWMH period setting signal terminal (CHG1ON).
The operation of the circuit of the third related art will be described with reference to the timing chart shown in FIGS. 26A to 26H. During the L period of the main PWM signal, the addition data of the adder 63 of the main circuit 5 is latched by the latch 2b in response to an H output of the AND gate 15b supplied with the system clock and data setting signal. The data latched by the latch 2b is inverted by the inverter 4b and inputted to the counter 1b. Since the counter 1bis in the load state, the inverted value of the data latched by the latch 2b is loaded in the counter 1b at the rise timing of the Q of DFF 9b inputted to the clock input terminal. When the output H of the main PWM signal or the Q output H of RSFF 5b by an external trigger is inputted to the OR gate 6b, the Q output of the latch 7b becomes H synchronously with the rise timing of the clock of the free-run counter 26 of the main circuit and the load state of the counter 1bis released. Thereafter, in response to the rise timing of the Q of DFF 9b, the counter 1b counts up and if a carry is outputted, the AND gate outputs H so that RSFF 17b outputs the main synchronism sub PWM signal of H (refer to t1, a, c, d, and h in FIGS. 26A to 26H). Thereafter, the main PWML period setting signal generated in response to the fall timing of the main PWM signal resets RSFFs 5b and 7b so that the main synchronism sub PWM signal becomes L (refer to t2, a, e, and h in FIGS. 26A to 26H). At the same time, the counter 1b again enters the load state. The data setting signal opens the gate of the buffer 3b so that the data latched by the latch 2b is inputted to the adder 63 of the main circuit. The new addition data of the adder 63 is inputted and set to the latch 2b in response to the output H of the AND gate 15b. The addition data set to the latch 2b is checked, from the Q output of DFF 13b supplied with an output of the comparator 12b, whether it is larger or smaller than the data before the addition at the main circuit. However, all data bits are inverted by the inverter 4b. Therefore, if the value of the set data increases, the carry generation time as from the count start of the counter 1b becomes late and the rise timing of the main synchronism sub PWM signal lags relative to the rise timing of the main PWM signal. Conversely, if the value of the set data decreases, the rising timing leads. In the system where the H period (term) of the main synchronism sub PWM signal elongates and the controlled power supply voltage Vin increases, the controlled power supply voltage Vin lob becomes larger than the comparison voltage Vref 11b and the output of DFF 13b becomes H, or vice versa. Therefore, in the addition calculation by the adder 63 of the main circuit, the data to be added is selected so as to increase the new data set to the latch when the output of DFF 13b is H or decrease it when L. In this manner, a negative feedback can be realized. The circuit of the third related art operates as described above.
The above operation will be described in detail with reference to the circuit shown in FIGS. 23A, 23B, 24A, 24B and 25. This circuit is modified from the circuit of the second related art. The different points reside in that AND gates 7-1 and 7-2 are added, the two-input OR gates 81 and 82 of the second related art are changed to three-input OR gates 81 and 82, the output terminal of the AND gate 7-1 is connected to the third input terminal of the OR gate 82, and the output terminal of the AND gate 7-2 is connected to the third input terminal of the OR gate 81. One input terminals of the AND gates 7-1 and 7-2 are inputted with PM1ONSS signal, and the other input terminals of the AND gates 7-1 and 7-2 are inputted with ST1B and ST1 signals, respectively. The timing circuit 53 has an additional signal output terminal for PM1ONSS signal which is outputted when PWM signal is off as shown in the timing chart of FIG. 17. A CRYOUT terminal is connected to the carry output terminal (C terminal) of the adder 63. The output terminal of the adder 63 is connected to ADROUT signal terminal (bus). The operation of increasing or decreasing the value of set data by the AND gates 7-1 and 7-2 and other circuits portions is similar to the operation of count up/down by "1" by the register 3 PWM1ON of the first related art. In the circuit shown in FIGS. 24A and 24B, when DFF 13b outputs ST1 of H at the timing of PM1ONSS, the AND gate 7-2 outputs H and O1H is supplied from the latch 8 to the adder 60 to count up by "1". When ST1B is H, the AND gate 7-1 outputs H and FFH is supplied from the latch 7 to the adder 63 to count down by "1".
Next, the maximum/minimum value limit control for the data to be set to the latch 2b will be described. This control is made by inhibiting an output of the AND gate 15b by an output of the composite gate 14b. It is therefore possible to prevent the data loaded to the counter during the L period of the main PWM signal from being changed from all H to all L or vice versa.
First, the maximum value limit control will be described. It is assumed that the data set to the latch 2b is all L. In response to the rise timing of the data setting signal, the gate of the buffer 3b is opened and the adder 63 of the main circuit starts the addition calculation. At the same time, when the Q output of H is outputted from DFF 13b (i.e., when it is instructed to reduce the value of the data set to the register 2b and elongate the H period of the main synchronism sub PWM signal), all L data set to the register 2b is subjected to subtraction (addition of FFH) by the adder 63 of the main circuit so that the adder 63 does not output a carry and the inverter 24b outputs H. The output of the inverter 24b and the Q output make the composite gate 14b output L. Therefore, an output of the AND gate 15b by the data setting signal and system clock is inhibited, and the gate of the latch 2b is not opened. As a result, the addition data is not set to the latch 2b and all L state is maintained. In the above manner, the maximum value limit control is completed.
Next, the minimum value limit control will be described. It is assumed that the data set to the latch 2b is all H. In response to the rise timing of the data setting signal, the addition calculation starts. At the same time, when the Q output of H is outputted from DFF 13b (i.e., when it is instructed to increase the value of the data set to the latch 2b and shorten the H period of the main synchronism sub PWM signal), all H data set to the latch 2b is subjected to addition by the adder 63 of the main circuit so that the adder 63 outputs a carry and the inverter 24b outputs H. A logical product of this carry and the Q output makes the composite gate 14b output L. Therefore, similar to the maximum value limit control, the minimum value limit control is completed.
Next, a protect operation for the external trigger input will be described with reference to the timing charts shown in FIGS. 27A to 27I. At the rise timing of the main PWM signal, the counter 18b enters the load state and the frequency divider circuit 19b and RSFF 20b are reset. By the Q output of L from RSFF 20b, an input of the external trigger signal is intercepted at the AND gate 22b. At the same time, the main PWMH period setting signal rises. A logical product of this signal and the system clock which rises after a half period of the main PWMH period setting signal after the rising timing, makes necessary protect data from CPU be loaded to the counter 18b. When the main PWM signal falls thereafter, the load and reset states are released, and the counter 18b starts counting an output of the frequency divider circuit 19b (refer to tl and a in FIGS. 27A to 27I). Thereafter, the counter 18b outputs a carry and the Q output of RSFF 20b becomes H to release the external trigger protect by the AND gate 22b (refer to t2, e, and f in FIGS. 27A to 27I).
As described above, according to the third related art, by using the rise timing of the power control PWM signal (main PWM signal) or the external trigger signal as a reference, the other PWM output (main synchronism sub PWM signal) can be generated with a simple circuit structure, the rise timing of the other PWM output being controlled through negative feedback of the controlled power supply voltage.
However, with the third related art, the operation of elongating or shortening the H period of the main synchronism sub PWM signal is affected by the operation of elongating or shortening the H period of the main PWM signal. A fidelity operation of counting up or down by "1" in accordance with feedback information cannot be realized except while the main PWM signal is in the maximum value limit state. Specifically, the data obtained by negative feedback control and loaded in the counter 1b of the main synchronism sub PWM generator unit is not correctly the data of the H period of the main synchronism sub PWM signal itself, but is the data representative of the period from the rise timing of the main PWM signal to the rise timing of the main synchronism sub PWM signal, and so the H period of the main synchronism sub PWM signal is determined indirectly. Therefore, if the main synchronism sub PWM generator unit updates data for elongating the H period through "1"-down of the time difference from the rise timing of the main PWM signal and if the H period of the main PWM signal has been changed by "1"-up, then the H period of the main synchronism sub PWM signal is changed by "2"-up. Conversely, if the H period of the main PWM signal has been changed by "1"-down, the H period of the main synchronism sub PWM signal does not change. Furthermore, if the main synchronism sub PWM generator unit updates data for shortening the H period through "1"-up of the time difference from the rise timing of the main PWM signal and if the H period of the main PWM signal has been changed by "1"-down, then the H period of the main synchronism sub PWM signal is changed by "2"-down. Conversely, if the H period of the main PWM signal has been changed by "1"-up, the H period of the main synchronism sub PWM signal does not change.